Transistor-level based defect tolerance for reliable nanoelectronics

Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by quaddedtransistor structure that guarantees defect tolerance of all single defects and a large number of multiple defects as validated by theoretical analysis and simulation. As demonstrated by extensive simulation results using ISCAS 85 and 89 benchmark circuits, the investigated technique achieves significantly higher defect tolerance than recently reported nanoelectronics defect-tolerant techniques (even with up to 4 to 5 times more transistor defect probability) and at reduced area overhead.

• Type: Conference
• Year: 2008
• Where: AICCSA
• Authors: Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki
• Keywords: AICCSA 2008, Defect Tolerance, Defect Tolerant Technique, Hardware, Transistor Defect Probability