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37

FPGA
2008
ACM

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FPGA interconnect design using logical effort

14 years 16 days ago

FPGA interconnect design using logical effort

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Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and gain more insight into how the parameters affect the result. In this paper, the LE model will be introduced and an application to FPGA interconnect driver sizing described. Simple closed form equations are given for delay, sensitivity of delay to driver size and optimal delay. The results are shown to closely agree with Spice simulations.

Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong

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Delay Models | FPGA | FPGA 2008 | FPGA Interconnect Driver | Optimal Delay |

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Added	26 Oct 2010
Updated	26 Oct 2010
Type	Conference
Year	2008
Where	FPGA
Authors	Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong

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