Architecture-specific packing for virtex-5 FPGAs

We consider packing in the commercial FPGA context and examine the speed, performance and power trade-offs associated with packing in a state-of-the art FPGA

• Type: Conference
• Year: 2008
• Where: FPGA
• Authors: Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal
• Keywords: Dual-output Lut Packing, FPGA, FPGA 2008, Large Ip Blocks, Logic Blocks