A versatile hardware architecture for a CFAR detector based on a linear insertion sorter

This paper presents a versatile hardware architecture that implements six variant of the CFAR detector based on linear and non-linear operations. Since some implemented CFAR detectors require sorting, a linear sorter based on a First In First Out (FIFO) schema is used. The proposed architecture can be used as a specialized module or coprocessor for Software Defined Radar (SDR) applications. The results of implementing the architecture on a Field Programmable Gate Array (FPGA) are presented and discussed.

• Type: Conference
• Year: 2008
• Where: FPL
• Authors: Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo
• Keywords: Cfar Detectors, Field Programmable Gate Array, FPL 2008, Hardware, Versatile Hardware Architecture