Comparing throughput and power consumption in both sequential and reconfigurable processors

Recent improvements in the memory capacity of Field Programmable Gate Arrays (FPGAs) have spurred interest in using the devices for arithmetic floating-point operations. However, adapting a program designed to run on a sequential processor to be run instead on an FPGA can be timeconsuming and difficult for anyone lacking significant experience in hardware design. In this paper we use a high-level

• Type: Conference
• Year: 2008
• Where: FPL
• Authors: Kevin K. Liu, Charles B. Cameron, Antal A. Sarkady
• Keywords: Arithmetic Floating-point Operations, FPL 2008, Hardware, Memory Capacity, Programmable Gate Arrays