A Novel High Speed Chinese Abacus Multiplier

—In this paper, a novel Chinese abacus multiplier is presented. The architecture of a 4-bit multiplier is demonstrated. The simulation results of our work are compared with the 4-bit Braun array multiplier. The 0.35µµµµm and 0.18µµµµm TSMC CMOS technologies are used in the simulation. The delay time of the abacus multiplier is at least 63% less than that of Braun array multiplier for 0.18µµµµm technology. The power consumption of the abacus multiplier is about 51% less than that of Braun array multiplier for 0.18µµµµm technology.

• Type: Conference
• Year: 2007
• Where: IMECS
• Authors: Yi-Chieh Lin, Chien-Hung Lin, Zi-Yi Zhao, Yu-Zhi Xie, Yen-Ju Chen, Shu-Chung Yi
• Keywords: Abacus Multiplier, Braun Array Multiplier, Chinese Abacus Multiplier, IMECS 2007, Theoretical Computer Science