Computing Lennard-Jones Potentials and Forces with Reconfigurable Hardware

Abstract-- Technological advances have made FPGAs an attractive platform for the acceleration of complex scientific applications. These applications demand high performance and highprecision floating point arithmetic. In this paper, we present a design for calculating the Lennard-Jones potential and force as is done in molecular dynamics simulations. This architecture employs IEEE 754 double precision floating point units, including a square root unit developed for this kernel. The design presented is a modular, very deeply pipelined architecture that exploits the fine-grained parallelism of the calculations. With the Xilinx Virtex-II Pro as a target device, an implementation using two pipelines operating in parallel achieves 3.9 GFLOPS.

• Type: Conference
• Year: 2004
• Where: ERSA
• Authors: Ronald Scrofano, Viktor K. Prasanna
• Keywords: ERSA 2004, ERSA 2007, Floating Point, Floating Point Arithmetic, Precision Floating Point