Architectural Support for Runtime 2D Partial Reconfiguration

: Traditional FPGA architectures can potentially allow the dynamic swap in and out of hardware tasks through 2D partial reconfiguration. A segmented bus structure is proposed to be superimposed on such architectures. Its purpose is to support connections between on-chip hardware tasks, or between hardware tasks and chip IO pads. The required area overhead is also estimated.

• Type: Conference
• Year: 2006
• Where: ERSA
• Authors: Fei Wang, Jack S. N. Jean
• Keywords: ERSA 2006, ERSA 2007, Hardware Tasks, On-chip Hardware Tasks, Traditional FPGA Architectures