Design and Implementation of a High Speed Microprocessor Simulator BurstScalar

This paper describes the design and implementation of our high speed simulator for out-of-order microprocessors named BurstScalar. The simulator is based on the wellknown SimpleScalar simulator but its execution speed is accelerated by computation reuse technique. Each time a loop is iterated, BurstScalar consults its state transition table to examine whether the iteration turns the microarchitectural state into what has already occurred. If the behavior of the iteration matches a state transition table entry, we reuse the complicated computation for out-of-order microarchitectural simulation by simply following the transition arc registered in the table. Moreover, in order to minimize the overhead of the reuse, we apply the reuse technique only to loops with enough number of iterations. This loop selection is performed by an instruction level pre-execution which only costs 1/10 to 1/100 of out-of-order cycle accurate simulation. The evaluation of BurstScalar with SPEC CPU95 benchmark...

• Type: Conference
• Year: 2004
• Where: MASCOTS
• Authors: Takashi Nakada, Hiroshi Nakashima
• Keywords: Computation Reuse Technique, MASCOTS 2004, MASCOTS 2007, Reuse Technique, State Transition Table