A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA

The availability of SiGe HBT devices has opened a door for Gigahertz FPGAs. However, the large device power consumption limits its scale. In order to solve this problem, a Multiple-Speed Current Mode Logic design has been developed to provide variable power (and speed) settings. The performance of the Multiple-Speed Current Mode Logic architecture at the optimum setting exhibits similar performance to conventional Current Mode Logic designs. The Multi-Speed FPGA has been developed based on this new design. The economic power setting (lower speed setting) does not degrade its performance substantially. With this power saving technique the Multiple-Speed FPGA, therefore, can be scaled up in the future. Key words: SiGe, HBT, CML, Power Saving architecture, FPGA.

• Type: Conference
• Year: 2003
• Where: ERSA
• Authors: Jong-Ru Guo, Chao You, Michael Chu, Kuan Zhou, Young Uk Yim, Robert W. Heikaus, Russell P. Kraft, John F. McDonald
• Keywords: Current Mode Logic, ERSA 2003, ERSA 2007, Mode Logic Designs, Multiple-Speed Current Mode