N-Tuple Compression: A Novel Method for Compression of Branch Instruction Traces

Branch predictors and processor front-ends have been the focus of a number of computer architecture studies. Typically they are evaluated separately from other components using trace-driven simulation based on instruction traces. To offer a faithful representation of processor’s workload the traces are very large, and hence difficult to manage if kept in uncompressed form. In order to reduce simulation overhead due to the processing of non-branch instructions, we propose a new form of instruction trace, the Branch Instruction Trace (BIT), suitable for simulation of dynamic branch prediction mechanisms, fetch engines, and trace caches. A novel method for lossless trace compression, which can be applied to both ASCII and binary BIT traces, is also introduced. The proposed method relies on the trace record table (TRT) consisting of unique trace records. The trace size can be reduced by replacing each trace record by its ID in the TRT, since the number of unique trace records is much le...

• Type: Conference
• Year: 2003
• Where: ISCAPDCS
• Authors: Aleksandar Milenkovic, Milena Milenkovic, Jeffrey H. Kulick
• Keywords: Instruction Trace, ISCAPDCS 2003, ISCAPDCS 2007, Trace Records, Unique Trace Records