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    VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault Descriptions

    14 years 7 days ago
    VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault Descriptions
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    Volkmar Sieh, Oliver Tschäche, Frank Balbach
    claim paper
    Added 01 Nov 2010
    Updated 01 Nov 2010
    Type Conference
    Year 1997
    Where FTCS
    Authors Volkmar Sieh, Oliver Tschäche, Frank Balbach
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