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PDPTA
2000

Constant Multipliers for FPGAs

14 years 10 days ago
Constant Multipliers for FPGAs
This paper presents a survey of techniques to implement multiplications by constants on FPGAs. It shows in particular that a simple and well-known technique, canonical signed recoding, can help design smaller constant multiplier cores than those present in current libraries. An implementation of this idea in Xilinx JBits is detailed and discussed. The use of the latest algorithms for discovering optimal chain of adders, subtractors and shifters for a given constant multiplication is also discussed. Exploring such solutions is made possible by the new FPGA programming frameworks based on generic programming languages, such as JBits, which allow an arbitrary amount of irregularity to be implemented even within an arithmetic core.
Florent de Dinechin, Vincent Lefèvre
Added 01 Nov 2010
Updated 01 Nov 2010
Type Conference
Year 2000
Where PDPTA
Authors Florent de Dinechin, Vincent Lefèvre
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