Microcode Generation for Flexible Parallel Target Architectures

: Advanced architectural features of microprocessors like instruction level parallelism and pipelined functional hardware units require code generation techniques beyond the scope of traditional compilers. Additionally, recent design styles in the area of digital signal processing pose a strong demand for retargetable compilation. This paper presents an approach to code generation based on netlist descriptions of the target processor. The basic features of the MSSQ microcode compiler are outlined, and novel techniques for handling complex hardware modules and multi-cycle operations are presented.1

• Type: Conference
• Year: 1994
• Where: IFIPPACT
• Authors: Rainer Leupers, Wolfgang Schenk, Peter Marwedel
• Keywords: Code Generation, Code Generation Techniques, Distributed And Parallel Computing, Functional Hardware Units, IFIPPACT 1994