Hyper-Systolic Matrix Multiplication

A novel parallel algorithm for matrix multiplication is presented. It is based on a 1-D hyper-systolic processor abstraction. The procedure can be implemented on all types of parallel systems.

• Type: Conference
• Year: 1996
• Where: PDPTA
• Authors: Thomas Lippert, Klaus Schilling
• Keywords: 1-D Hyper-systolic Processor, Matrix Multiplication, Parallel Systems, PDPTA 1996, PDPTA 2007