A Host Interface Architecture for High-Speed Networks

This paper describes a new host interface architecture for high-speed networks operating at 800 of Mbit/second or higher rates. The architecture is targeted to achieve several 100s of Mbit/second application-to-application performance for a wide range of host architectures. The architecture achieves the goal by providing a streamlined execution environment for the entire path between host application and network interface. In particular, a "Communication Accelerator Block" (CAB) is used to minimize data copies, reduce host interrupts, support DMA and hardware checksumming, and control network access. This host architecture is applicable to a large class of hosts with high-speed I/O busses. Two implementations for the 800 Mbit/second HIPPI network are under development. One is for a distributed-memory supercomputer (iWarp) and the other is for a high-performance workstation (DECstation 5000). We describe and justify both implementations. Keyword Codes: B.4.1; C.2.1

• Type: Conference
• Year: 1992
• Where: HPN
• Authors: Peter Steenkiste, Brian Zill, H. T. Kung, Steven Schlick, Jim Hughes, Bob Kowalski, John Mullaney
• Keywords: Host Architecture, Host Interface Architecture, Host Interrupts, HPN 1992, HPN 1998