—This paper presents a compact analog neuron cell with an array of charge-coupled synapses connected via a common output terminal. Synaptic responses are fed into a current mirror, the summing point of the neuron. A couple of CMOS inverters are employed to implement the temporal and spatial integration of weighted input spikes generated by the synaptic array. The decay of the membrane potential is mimicked by the charge leakage through a reversebiased diode, whose model is verified by comparing the simulations and measured data. Spice simulation results show that the proposed neuron cell is capable of capturing the summing and thresholding dynamics of biological neurons.