Energy efficient implementation of parallel CMOS multipliers with improved compressors

Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under varying constraints. It is shown that Non-Booth multipliers start to become more energy efficient for strict delay targets. In addition, novel 3:2 and 4:2 compressors are presented to save energy at the same target delay. The proposed compressors provide up to 20% energy reduction depending on the target delay at 65nm CMOS technology. Non-Booth multiplier implemented with the proposed compressors provides performance advantage as the voltage is scaled from its nominal value. Further, we examined all designs in 45nm, 32nm and 22nm CMOS technology nodes. Categories and Subject Descriptors B.2.4 [High-Speed Arithmetic]: Cost/performance; B.6.1 [Design Styles]: Combinational logic, Parallel Circuits; B.7.1 [Types and Design Styles]: VLSI (very large scale integration) General Terms Algorithm, Design, Performance...

• Type: Conference
• Year: 2010
• Where: ISLPED
• Authors: Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija
• Keywords: Design, Hardware, ISLPED 2010, Non-booth Multiplier, Target Delay