High-throughput bayesian computing machine with reconfigurable hardware

We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic graph) topology. Our BCM achieves high throughput by exploiting the FPGA's distributed memories and abundant hardware structures (such as long carry-chains and registers), which enables us to 1) develop an innovative memory allocation scheme based on a maximal matching algorithm that completely avoids memory stalls, 2) optimize and deeply pipeline the logic design of each processing node, and 3) schedule them optimally. The BCM architecture not only can be applied to many important algorithms in artificial intelligence, signal processing, and digital communications, but also has high reusability, i.e., a new application needs not change a BCM's hardware design, only new task graph processing and code compilation are necessary. Moreover, the throughput of a BCM scales almost linearly with the size of t...

• Type: Conference
• Year: 2010
• Where: FPGA
• Authors: Mingjie Lin, Ilia Lebedev, John Wawrzynek
• Keywords: Bayesian Computing Machine, FPGA, FPGA 2010, Reconfigurable Hardware, Throughput Bayesian Computing