From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers

Parallel processors such as SIMD computers have been successfully used in various areas of high performance image and data processing. Due to their characteristics of highly regular structures and mainly local interconnections, SIMD or SIMD-like architectures have been proposed for a large-scale integration of recently developed quantum and nanoelectronic devices. In this paper, we present a fault-tolerant technique suitable for an implementation in nanoelectronics, the triplicated interwoven redundancy (TIR). The TIR is a general class of triple modular redundancy (TMR), but implemented with random interconnections. A prototype structure for an image processor is proposed for the implementation of the TIR technique and a simulation based reliability model is used to investigate its faulttolerance. The TIR is extended to higher orders, namely, the N-tuple interwoven redundancy (NIR), to achieve higher system reliabilities. It is shown that the reliability of a general TIR circuit is, i...

• Type: Conference
• Year: 2004
• Where: ICPR
• Authors: Jie Han, Pieter Jonker
• Keywords: Computer Vision, General Tir Circuit, ICPR 2004, Interwoven Redundancy, TIR Technique