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IJNSEC
2008

Parallel Hardware Architectures for the Cryptographic Tate Pairing

13 years 11 months ago
Parallel Hardware Architectures for the Cryptographic Tate Pairing
Identity-based cryptography uses pairing functions,which are sophisticated bilinear maps defined on elliptic curves.Computing pairings efficiently in software is presently a relevant research topic. Since such functions are very complex and slow in software, dedicated hardware (HW) implementations are worthy of being studied, but presently only very preliminary research is available. This work affords the problem of designing parallel dedicated HW architectures, i.e.,co-processors, for the Tate pairing, in the case of the Duursma-Lee algorithm in characteristic 3. Formal scheduling methodologies are applied to carry out an extensive exploration of the architectural solution space, evaluating the obtained structures by means of different figures of merit such as computation time, circuit area and combinations thereof.Comparisons with the (few) existing proposals are carried out, showing that a large space exists for the efficient parallelHW computation of pairings.
Guido Marco Bertoni, Luca Breveglieri, Pasqualina
Added 12 Dec 2010
Updated 12 Dec 2010
Type Journal
Year 2008
Where IJNSEC
Authors Guido Marco Bertoni, Luca Breveglieri, Pasqualina Fragneto, Gerardo Pelosi
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