A Timed Failure Equivalence Preserving Abstraction for Parametric Time-interval Automata

ion for Parametric Time-Interval Automata Akio Nakata, Tadaaki Tanimoto, Suguru Sasaki, Teruo Higashino Department of Information Networking, Graduate School of Information Science and Technology, Osaka University, Suita, Osaka 565-0871, Japan In the development of real-time communicating hardware/embedded-software systems, it is frequently the case that we want to refine/optimize the system's internal behavior while preserving the external timed I/O behavior. In such a design refinement, modification of the systems' internal branching structures, as well as re-scheduling of internal actions, may frequently occur. Our goal is, then, to ensure that such modification of internal branching structures and re-scheduling of internal actions preserve the systems' external timed behavior, which is typically formalized by the notion of (timed) failure equivalence since it is less sensitive to the difference of internal branching structures than (timed) weak bisimulation. In orde...

• Type: Journal
• Year: 2006
• Where: IJFCS
• Authors: Akio Nakata, Tadaaki Tanimoto, Suguru Sasaki, Teruo Higashino
• Keywords: External Timed Behavior, IJFCS 2006, Internal Actions, Internal Branching Structures