Efficient implementation of 3X for radix-8 encoding

Several commercial processors have selected the radix-8 multiplier architecture to increase their speed, thereby reducing the number of partial products. Radix-8 encoding reduces the digit number length in a signed digit representation. Its performance bottleneck is the generation of the term 3X, also referred to as hard multiple. This term is usually computed by an adding and shifting operation, 3X

• Type: Journal
• Year: 2008
• Where: MJ
• Authors: Gustavo A. Ruiz, Mercedes Granda
• Keywords: Digit Number Length, MJ 2008, Radix-8 Multiplier Architecture, Several Commercial Processors