Stringent memory access and search speed requirements are two of the main bottlenecks in wire speed processing. Most viable search engines are implemented in content addressable memories (CAMs). CAMs have high operational speed advantage over other memory search algorithms. However, this performance advantage comes with a price of higher silicon area, and higher power consumption. Ternary CAMs (TCAM) are widely used for route lookup operations in networking applications. IP address prefix length distribution in the core routers shows a similar characteristic such that the prefixes with 24 or longer bits attract more than 50% of the traffic. Based on this statistical observation, we propose a TCAM architecture that can be used on top of the previously reported power saving techniques and it offers additional 30% reduction in power consumption. Furthermore, we model the dynamic power consumption in TCAM circuits due match, mismatch and don't care activities.