A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip

Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components, mixedsignal I/O cores) in a single silicon die. The large number of resources that have to communicate makes the use of interconnection systems based on shared buses inefficient. One way to solve the problem of on-chip communications is to use a Network-on-Chip (NoC)-based communication infrastructure. Such interconnection systems offer new degrees of freedom, exploration of which may reveal significant optimization possibilities: the possibility of arranging the computing and storage resources in an NoC, for example, has a great impact on various performance indexes. The paper addresses the problem of topological mapping of intellectual properties (IPs) on the tiles of a mesh-based NoC architecture. The aim is to obtain the Pareto mappings that maximize performance and minimize power dissipation. We propos...

• Type: Journal
• Year: 2006
• Where: JUCS
• Authors: Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
• Keywords: Great Impact, Interconnection Systems, JUCS 2006, Mesh-based Noc Architectures