Design Automation of Real-Life Asynchronous Devices and Systems

The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks is becoming impossible. In static timing analysis process variations and signal integrity issues stretch the timing margins to the point where they become too conservative and result in significant overdesign. Importance and difficulty of such problems push some developers to once again turn to asynchronous alternatives. However, the electronics industry for the most part is still reluctant to adopt asynchronous design (with a few notable exceptions) due to a common belief that we still lack a commercial-quality Electronic Design Automation tools (similar to the synchronous RTL-to-GDSII flow) for asynchronous circuits. 

• Type: Journal
• Year: 2007
• Where: FTEDA
• Authors: Alexander Taubin, Jordi Cortadella, Luciano Lavagno, Alex Kondratyev, Ad M. G. Peeters
• Keywords: Asynchronous, FTEDA 2007, Static Timing Analysis, Timing Margins