Efficient hardware code generation for FPGAs

r acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach in ROCCC. The smart buffer is a component that reuses input data between adjacent iterations. It significantly improves the performance of the circuit and simplifies loop control. The ROCCC-generated data-path can execute one loop iteration per clock-cycle when there is no loop-dependency or there is only scalar recurrence variable dependency. ROCCC's approach to supporting while-loops operating on scalars makes the compiler able to move scalar iterative computation into hardware. Categories and Subject Descriptors: B.5 [Register-transfer-level Implementation]; B.5.2 [Design Aids]; C.3 [Signal Processing Systems] General Terms: Design, Languages, Performance Additional Key Words and Phrases: Reconfigurable Computing, High-level Synthesis, Data Reuse, FPGA, VHDL ____________________________________________...

• Type: Journal
• Year: 2008
• Where: TACO
• Authors: Zhi Guo, Walid A. Najjar, Betul Buyukkurt
• Keywords: Code Generation Approach, Recurrence Variable Dependency, Scalar Iterative Computation, TACO 2008