A high performance architecture of elliptic curve scalar multiplication over finite field GF(2m ) is proposed. A pseudo-pipelined word serial finite field multiplier with word size w, suitable for the scalar multiplication is also developed. Implemented in hardware, this system performs a scalar multiplication in approximately 6m/w(m - 1) clock cycles and the gate delay in the critical path is equal to TAND + (log2 w)TXOR, where TAND and TXOR are delays due to two-input AND and XOR gates respectively.
B. Ansari, M. A. Hasan