Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration

Abstract--Multimedia and DSP applications have several computationally intensive kernels which are often offloaded and accelerated by application-specific hardware. This paper presents a speculative loop pipelining technique to overcome limitations of binary translation for hardware acceleration. Although many compilers have been developed at source level, it is desirable to translate the binary targeted to popular processors onto hardware for several practical benefits. However, the translated code can be less optimized. In particular, it is difficult to optimize memory accesses on binary to exploit pipeline parallelism since memory optimization techniques require perfect dependence information for correctness and efficiency. This information is not often available at binary level or even at the source level. Our technique synthesizes the pipeline with memory dependence speculation and postpones some phases of compilation by generating a small dependence analysis code or logic which m...

• Type: Journal
• Year: 2008
• Where: TCAD
• Authors: Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozorgzadeh
• Keywords: Hardware, Memory Dependence Speculation, Source Level, TCAD 2008