Variability-Aware Bulk-MOS Device Design

As CMOS technology is scaled down toward the nanoscale regime, drastically growing leakage currents and variations in device characteristics are becoming two important design challenges. Traditionally, the device-design methodology is based on finding the device parameters which minimize the leakage current while providing a minimum saturation current for the transistor. This methodology may change when variations are accounted for design. In this paper, a novel device optimization methodology is presented that incorporates variability awareness into the device-design flow such that the designed device satisfies desired bounds on total leakage, saturation current, and intrinsic delay under parameter variabilities. The technique locates the maximum-yield rectangular cube in the 5-D feasible space composed of oxide-thickness, gate-length, and channel-doping profile parameters. The center of this cube is considered as the maximum-yield design point with the highest immunity against variat...

• Type: Journal
• Year: 2008
• Where: TCAD
• Authors: Javid Jaffari, Mohab Anis
• Keywords: Device Optimization Methodology, Leakage Currents, Methodology, TCAD 2008