Queue computers are a viable option for embedded systems design. Queue computers feature a dense instruction set, high parallelism, low hardware complexity. In this paper we propose an optimization technique to reduce the overhead of long reaching definitions of variables in queue processors. Long reaching definitions have direct relationship with the queue register file utilization of the processor, and also to the bits in the instruction set reserved to reference operands. Using integer and embedded benchmarks, we demonstrate that our technique effectively reduces the length of reaching definitions up to 90%.
Yuki Nakanishi, Arquimedes Canedo, Ben A. Abderaze