Fully Parallel Stochastic LDPC Decoders

Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stochastic low-density parity-check (LDPC) decoders. To obtain the characteristics of the proposed architecture, we apply this architecture to decode an irregular state-of-the-art (1056,528) LDPC code on a Xilinx Virtex-4 LX200 field-programmable gate-array (FPGA) device. The implemented decoder achieves a clock frequency of 222 MHz and a throughput of about

• Type: Journal
• Year: 2008
• Where: TSP
• Authors: Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gross
• Keywords: Architecture, Iterative Decoding, Parallel Stochastic Low-density, TSP 2008