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24

CAI
2004
Springer

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A Generic Dual Core Architecture with Error Containment

13 years 10 months ago

A Generic Dual Core Architecture with Error Containment

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The dual core strategy allows to construct a fail-silent processor from two instances (master/checker) of any arbitrary standard processor. Its main drawbacks are its vulnerability with respect to common mode failures and the existence of residual single points of failure. In this paper we propose a generic frame that systematically eliminates these drawbacks. First, we employ temporal redundancy to cope with common mode failures. Unlike similar approaches we can ensure error containment even if

Thomas Kottke, Andreas Steininger

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CAI 2004 | Common Mode Failures | Information Technology | Single Points | Temporal Redundancy |

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Added	16 Dec 2010
Updated	16 Dec 2010
Type	Journal
Year	2004
Where	CAI
Authors	Thomas Kottke, Andreas Steininger

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