A Generic Dual Core Architecture with Error Containment

The dual core strategy allows to construct a fail-silent processor from two instances (master/checker) of any arbitrary standard processor. Its main drawbacks are its vulnerability with respect to common mode failures and the existence of residual single points of failure. In this paper we propose a generic frame that systematically eliminates these drawbacks. First, we employ temporal redundancy to cope with common mode failures. Unlike similar approaches we can ensure error containment even if

• Type: Journal
• Year: 2004
• Where: CAI
• Authors: Thomas Kottke, Andreas Steininger
• Keywords: CAI 2004, Common Mode Failures, Information Technology, Single Points, Temporal Redundancy