Testable Path Delay Fault Cover for Sequential Circuits

We present an algorithm for identifyinga set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently aect the performance of the circuit or no test can be generated for them. To nd such faults, our methodology takes advantage of the sequential behavior of the circuit as well as of the information about uncontrollable signals in the sequential circuit. It can handle sequential circuits described as two- or multi-level netlists. The outcome of applying our methodology is smaller fault set and possibly smaller test set. We present experimental results on several ISCAS 89 benchmark circuits demonstrating that a large number of path delay faults in these circuits either cannot or does not have to be examined for delay defects.

• Type: Journal
• Year: 2000
• Where: JISE
• Authors: Angela Krstic, Srimat T. Chakradhar, Kwang-Ting Cheng
• Keywords: Delay Faults, Faults, JISE 2000, Sequential