The day Sherlock Holmes decided to do EDA

Semiconductor design companies are in a continuous search for design tools that address the ever increasing chip design complexity coupled with strict time-to-market schedules and budgetary constraints. A fundamental aspect of the design process that remains primitive is that of debugging. It takes months to close, it introduces costs and it may jeopardize the release date of the chip. This paper reviews the debugging problem and the research behind it over the past 20 years. The case for automated RTL debug tools and methodologies is also made to help ease the manual burden and complement current industrial verification practices. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids--Simulation, Verification General Terms Design, Verification Keywords Debugging, Error Localization, Verification

• Type: Conference
• Year: 2009
• Where: DAC
• Authors: Andreas G. Veneris, Sean Safarpour
• Keywords: Chip Design Complexity, DAC 2009, Design Automation, Industrial Verification Practices, Verification General Terms