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DAC
2009
ACM

Online cache state dumping for processor debug

15 years 5 days ago
Online cache state dumping for processor debug
Post-silicon processor debugging is frequently carried out in a loop consisting of several iterations of the following two key steps: (i) processor execution for some duration, followed by (ii) dumping out of the processor's internal state into an external logic analyzer for further offline processing. Internal state of the processor is dominated by the L2 cache. During the process of dumping the cache content, the processor's execution is halted so that the state can be faithfully reproduced offline. In order to reduce the duration for which the processor is halted, and indirectly reduce debug time, we propose two Online Cache Dumping strategies, Retransmit Non-dumped Line (RNL) and Dump History Table (DHT), with the objective of transferring the cache contents while the processor is executing, and yet maintaining fidelity of the dumped data. For typical experimental debug scenarios, we observe that the effective dump times are reduced to between 0.01% and 3.5% of the origi...
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishna
Added 12 Nov 2009
Updated 12 Nov 2009
Type Conference
Year 2009
Where DAC
Authors Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan
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