IPR: An Integrated Placement and Routing Algorithm

Abstract-- In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all previous placement approaches optimize some very primitive interconnect models during placement. These models are far from the actual interconnect implementation in the routing stage. As a result, placement solution considered to be good by primitive interconnect models may turn out to be poor after routing. In addition, the placement may not even be routable and timing closure may not be achievable. In this paper, we propose to address the inconsistency between the placement and routing objectives by fully integrating global routing into placement. As a first attempt to this novel approach, we focus on routability issue. We call the proposed algorithm for routing congestion minimization IPR (Integrated Placement and Routing). To ensure the algorithm to be computationally efficient, efficient placement and r...

• Type: Conference
• Year: 2007
• Where: DAC
• Authors: Min Pan, Chris C. N. Chu
• Keywords: DAC 2007, Design Automation, Global Routing Wirelength, Performance KEYWORDS Placement, Primitive Interconnect Models