Emerging single-chip heterogeneous multiprocessors feature hundreds of design elements contending for shared resources, making it difficult to isolate performance impacts of individual design changes. This work is the first to parameterize shared resource accesses in the form of access attributes, summarizing the impact of shared resource contention on system performance, analogous to the way RTL parameters summarize more detailed transistor models. The intuition behind access attributes is that much application and architecture dependent contention information is known during detailed cycle-accurate simulations, and would be useful to inform a higher level model. The detailed contention information is sampled from a short cycle-accurate simulation, "training" a high-level statistical regression model of contention. This contention model can then be used in simulation to estimate the impact of shared resource accesses at a el of abstraction, enabling the designers to explore...
Alex Bobrek, JoAnn M. Paul, Donald E. Thomas