GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches

In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous poweraware technology mapping algorithms for FPGAs have not taken into account the glitch power reduction. In this paper, we present a dynamic power estimation model and a new technology mapping algorithm considering glitches. To the best of our knowledge, this is the first work that explicitly reduces glitch power during technology mapping for FPGAs. Experiments show that our algorithm, named GlitchMap, is able to reduce dynamic power by 18.7% compared to a previous state-of-the-art power-aware algorithm, EMap [2]. Categories and Subject Descriptors J.6 [Computer-Aided Engineering]: Computer Aided Design General Terms Algorithm, Design, Experimentation Keywords FPGA technology mapping, dynamic power, glitch

• Type: Conference
• Year: 2007
• Where: DAC
• Authors: Lei Cheng, Deming Chen, Martin D. F. Wong
• Keywords: DAC 2007, Design Automation, Dynamic Power, Dynamic Power Consumption, Dynamic Power Estimation