Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization

Power gating is one of the most effective ways to reduce leakage power. In this paper, we introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep transistor networks from a temporal viewpoint. Based on this relationship, we propose an algorithm to reduce the total sizes of sleep transistors in Distributed Sleep Transistor Network designs. On average, the proposed method can achieve 21% reduction in the sleep transistor size. Categories and Subject Descriptors B.8.2 [Performance and Reliability]: Performance Analysis and Design Aids General Terms Performance, Design Keywords Leakage Current, Power Gating, IR Drop

• Type: Conference
• Year: 2007
• Where: DAC
• Authors: De-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih-Chieh Chang
• Keywords: DAC 2007, Design Automation, Power Gating, Sleep Transistor Network, Sleep Transistor Size