Hierarchical buffered routing tree generation

Abstract--This paper presents a solution to the problem of performance-driven buffered routing tree generation for VLSI circuits. Using a novel bottom-up construction algorithm and a local neighborhood search strategy, our polynomial time algorithm finds the optimum solution in an exponential-size solution subspace. The final output is a buffered rectilinear Steiner routing tree that connects the driver of a net to its sink nodes. The two variants of the problem, i.e., maximizing the required time at the driver subject to a maximum total area constraint and minimizing the total area subject to a minimum required time at the driver constraint, are handled by propagating three-dimensional solution curves during the construction phase. Experimental results demonstrate the effectiveness of our algorithm compared to other techniques.

• Type: Journal
• Year: 2002
• Where: TCAD
• Authors: Amir H. Salek, Jinan Lou, Massoud Pedram
• Keywords: Performance-driven Buffered Routing, Solution, TCAD 2002, Total Area