Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip

Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single global clock signal throughout a chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design is considered for achieving low power consumption and modular design. Such a design style fits nicely with the concept of voltage-frequency islands (VFIs) which has been recently introduced for achieving fine-grain system-level power management. This paper proposes a design methodology for partitioning an NoC architecture into multiple VFIs and assigning supply and threshold voltage levels to each VFI. Simulation results show about 40% savings for a real video application and demonstrate the effectiveness of our approach in reducing the overall system energy consumption. The results and functional correctness are validated using an FPGA prototype for a...

• Type: Conference
• Year: 2007
• Where: DAC
• Authors: Ümit Y. Ogras, Diana Marculescu, Puru Choudhary, Radu Marculescu
• Keywords: DAC 2007, Design Automation, Energy Consumption, Low Power Consumption, Major Design Bottlenecks