Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors

Three-Dimensional integration provides a simultaneous improvement in wire-related delay and power consumption of microprocessor circuits. Prior work has looked at the performance, power, and area benefits of 3D integration technology. In this paper, we investigate the scalability issues of 3D die-stacked arithmetic units. We explore the behavior of the 3D-integrated arithmetic circuits with increasing issue-width (parallel execution capability), transistor sizing, and temperature. We show that the 3D-integrated units have a lower latency degradation and lower rate of increase in energy consumption than planar circuits with increasing issue-widths and operating temperatures. We demonstrate that the 3D-integrated circuits have less sensitivity to transistor sizing than the planar circuits. Categories and Subject Descriptors B.2.2 [Hardware]: Performance Analysis and Design Aids General Terms Design, Die-stacked 3D integration, Arithmetic unit Keywords Issue-width, Scalability, Frequency...

• Type: Conference
• Year: 2007
• Where: DAC
• Authors: Kiran Puttaswamy, Gabriel H. Loh
• Keywords: 3D-integrated Arithmetic Circuits, DAC 2007, Design Automation, Microprocessor Circuits, Planar Circuits