Fast Min-Cost Buffer Insertion under Process Variations

Process variation has become a critical problem in modern VLSI fabrication. In the presence of process variation, buffer insertion problem under performance constraints becomes more difficult since the solution space expands greatly. We propose efficient dynamic programming approaches to handle the min-cost buffer insertion under process variations. Our approaches handle delay constraints and slew constraints, in trees and in combinational circuits. The experimental results demonstrate that in general, process variations have great impact on slew-constrained buffering, but much less impact on delay-constrained buffering, especially for small nets. Our approaches have less than 9% runtime overhead on average compared with a single pass of deterministic buffering for delay constrained buffering, and get 56% yield improvement and

• Type: Conference
• Year: 2007
• Where: DAC
• Authors: Ruiming Chen, Hai Zhou
• Keywords: Approaches Handle Delay, DAC 2007, Delay Constrained Buffering, Design Automation, Deterministic Buffering