On-chip decoupling capacitor optimization using architectural level prediction

Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular technique to counter this issue involves the usage of decoupling capacitors. This paper presents a novel design technique for sizing and placing on-chip decoupling capacitors based on activity signatures from the microarchitecture. Simulation of a typical processor workload (SPEC95) provides a realistic stimulation of microarchitecture elements that is coupled with a spatial power grid model. Evaluation of the proposed technique on typical microprocessor implementations (the Alpha 21264 and the Pentium II) indicates that this technique can produce up to a 30% improvement in maximum noise levels over a uniform decoupling capacitor placement strategy.

• Type: Journal
• Year: 2002
• Where: TVLSI
• Authors: Mondira Deb Pant, Pankaj Pant, D. Scott Wills
• Keywords: Activity-generated Power-supply Grid-noise, Decoupling Capacitor, On-chip Decoupling Capacitors, TVLSI 2002