Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique

Concurrent error detection (CED) based on time redundancy entails performing the normal computation and the re-computation at different times and then comparing their results. Time redundancy implemented can only detect transient faults. We present two algorithm-level time-redundancy-based CED schemes that exploit register transfer level (RTL) implementation diversity to detect transient and permanent faults. At the RTL, implementation diversity can be achieved either by changing the operation-to-operator allocation or by shifting the operands before re-computation. By exploiting allocation diversity and data diversity, a stuck-at fault will affect the two results in two different ways. The proposed schemes yield good fault detection probability with very low area overhead. We used the synopsys behavior complier (BC), to validate the schemes.

• Type: Journal
• Year: 2002
• Where: TVLSI
• Authors: Ramesh Karri, Kaijie Wu
• Keywords: Concurrent Error Detection, Implementation Diversity, Time Redundancy, TVLSI 2002