A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops

This paper compares four previously published static dual-edge-triggered flip-flops (DETFFs) with a proposed design for their performance, power dissipation, and low-voltage low-power applications. For each DETFF, the optimal delay, power consumption, and power-delay product are determined as the primary figures of merit. The proposed design is shown to have the least energy at low voltages.

• Type: Journal
• Year: 2002
• Where: TVLSI
• Authors: Wai Chung, Timothy Lo, Manoj Sachdev
• Keywords: Low-voltage Low-power Applications, Optimal Delay, Power Dissipation, TVLSI 2002