Automated energy calculation and estimation for delay-insensitive digital circuits

With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes a procedure to simulate a transistor-level design using a VHDL testbench, and then presents a fast and efficient energy estimation approach for delay-insensitive (DI) systems, based on gate-level switching. Specifically, the VHDL testbench reads the transistor-level design’s outputs and supplies the inputs accordingly, also allowing for automatic checking of functional correctness. This type of transistor-level simulation is absolutely necessary for asynchronous circuits because the inputs change relative to handshaking signals, which are not periodic, instead of changing relative to a periodic clock pulse, as do synchronous systems. The method further supports automated calculation of power and energy metrics. The energy estimation approach produces results three orders of magnitude faster than transist...

• Type: Journal
• Year: 2007
• Where: MJ
• Authors: Venkat Satagopan, Bonita Bhaskaran, Anshul Singh, Scott C. Smith
• Keywords: Energy Estimation Approach, Functional Correctness, MJ 2007, VHDL Testbench