Abstract—Power modeling based on performance monitoring counters (PMCs) has attracted the interest of many researchers since it become a quick approach to understand and analyse power behavior on real systems. Moreover, several power aware policies use power models to guide their decisions and to trigger low-level mechanisms -e.g. manage processor frequency-. Hence, the information, the accuracy and the capacity for detecting power phases that a model provides is critical to increase the power-aware research chances and to improve the success of power savings techniques based on such models. In addition, the design of current processors have varied considerably with the inclusion of multiple cores with some resources shared on a single die. As a result, PMC-based power models warrant further investigation on current energy-efficient multicore processors. In this paper, we present a methodology to produce decomposable PMC-based power models on current multicore architectures. Besides...