MorphoSys: case study of a reconfigurable computing system targeting multimedia applications

In this paper, we present a case study for the design, programming and usage of a reconfigurable system-on-chip, MorphoSys, which is targeted at computation-intensive applications. This 2-million transistor design combines a reconfigurable array of cells with a RISC processor core and a high bandwidth memory interface. The system architecture, software tools including a scheduler for reconfigurable systems, and performance analysis (with impressive speedups) for target applications are described. Keywords Reconfigurable processors, SIMD, dynamic configuration, automatic target recognition, scheduling, MPEG-2

• Type: Conference
• Year: 2000
• Where: DAC
• Authors: Hartej Singh, Guangming Lu, Eliseu M. Chaves Filho, Rafael Maestre, Ming-Hau Lee, Fadi J. Kurdahi, Nader Bagherzadeh
• Keywords: DAC 2000, Design Automation, Keywords Reconfigurable Processors, Reconfigurable Array, Reconfigurable System-on-chip